1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory constituted of a number of memory banks each including a plurality of lateral memory cells.
2. Description of Related Art
Referring to FIG. 1, there is shown an equivalent circuit diagram of one example of a ROM (read only memory) having a conventional lateral memory cell structure, which is disclosed in Japanese Patent Application Laid-open Publication No. JP-A-05-167042 and its corresponding U.S. Pat. No. 5,392,233, the disclosure of which is incorporated by reference in its entirety into this application. FIG. 1 shows only one memory cell bank of a number of memory cell banks provided in one semiconductor memory.
In one unitary bank constituted of a plurality of memory cells, a plurality of diffused layer wirings L1 to L5 are located in parallel to each other and separately from each other. Of these diffused layer wirings, the diffused layer wiring L1 is connected through a block selection transistor BT6 to a main ground line VG1, and the diffused layer wiring L2 has opposite ends thereof connected through block selection transistors BT2 and BT4 to a main bit line D1 and the main ground line VG1, respectively. The diffused layer wiring L3 is connected through a block selection transistor BT1 to the main bit line D1, and the diffused layer wiring L4 has opposite ends thereof connected through block selection transistors BT3 and BT5 to the main bit line D1 and another main ground line VG2, respectively. The diffused layer wiring L5 is connected through a block selection transistor BT7 to the main ground line VG2.
The block selection transistor BT1 has a gate electrode thereof connected to a block selection line S1, and each of the block selection transistors BT2 and BT3 has a gate electrode thereof connected to a block selection line S2. Each of the block selection transistors BT4 and BT5 has a gate electrode thereof connected to a block selection line S3, and each of the block selection transistors BT6 and BT7 has a gate electrode thereof connected to a block selection line S4.
Between the block selection line S2 and the block selection line S3, a plurality of words lines W1 to Wn are located in parallel to each other but perpendicular to the diffused layer wirings L1 to LS, and a memory cell transistor (M1, M2, M3, M4, . . . ) is formed at each of intersections between the words lines W1 to Wn and a region between each pair of adjacent diffused layer wirings. Accordingly, one unitary block is constituted of a memory cell matrix having "n" rows and four columns. A gate of memory cell transistors in one row are connected to a corresponding one of the word lines. Each memory cell transistor has either a high threshold or a low threshold in accordance with data written into the memory, so that when the word line connected to the gate of the memory cell transistor is brought to a high level, the memory cell transistor is put in an ON condition or in an OFF condition, dependently upon whether the memory cell transistor has either the high threshold or the low threshold.
Now, operation of the memory cell bank shown in FIG. 1 will be described. For example, when the memory cell M1 is read out, firstly, one main bit line D1 and two main ground lines VG1 and VG2 are selected by a Y decoder (not shown) in order to select one memory bank. As the result of the selection of these three wirings, the main bit line D1 is connected to a sense amplifier SA, and one of the two main ground lines VG1 is connected to ground, and the other of the two main ground lines VG2 is connected to a precharge circuit 10 so that the main ground line VG2 is charged by the precharge circuit 10.
Next, the block selection line S2 is brought to a high level so as to turn on the block selection transistor BT2; so that the diffused layer wiring L2 connected to a drain of the memory cell M1 to be selected, is connected to the main bit line D1. Similarly, the block selection line S4 is brought to a high level so as to turn on the block selection transistor BT6, so that the diffused layer wiring L1 connected to a source of the memory cell M1 to be selected, is connected to the main ground line VG1. Finally, by action of an X decoder (not shown), the word line W1 connected to the gate of the memory cell M1 to be selected, is brought to a high level, and the other word lines are brought to a low level. Thus, there is formed a current path starting from the main bit line D1 and reaching the main ground line VG1 connected to the ground, as shown by a broken line 1 in FIG. 1, so that a discharge current I1 flows from a current source (not shown) provided in the sense amplifier SA connected to the main bit line D1.
At this time, the block selections S1 and S3 are maintained at a low level, so that the block selection transistors BT1 and BT4 are off, so as to prevent formation of another current path. Furthermore, when the memory cell M1 is selected, there is simultaneously formed a current path starting from the main bit line D1 through the memory cell M4 to reach the main ground line VG2, as shown by a one-dot chain line 2 in FIG. 1. However, since the main ground line VG2 is charged by the precharge circuit 10, no substantial potential difference occurs between the main bit line D1 and the main ground line VG2. Therefore, a discharge current I2 flowing in the current path 2 is negligible as compared with the discharge current I1 flowing in the current path 1.
The discharge current I1 is small when a resistance value of the memory cell M1 is high, namely, when the threshold voltage of the memory cell M1 is high. The discharge current I1 is large when a resistance value of the memory cell M1 is low, namely, when the threshold voltage of the memory cell M1 is low. Therefore, by detecting this current by the sense amplifier SA, it is possible to read out information written in the memory cell M1.
At the time of reading the memory cell M2, the block selection transistors BT1 and BT4 are turned on, and the block selection transistors BT2 and BT6 are turned off. Furthermore, at the time of reading the memory cell M3 or M4, the main ground line VG1 is connected to the precharge circuit 20 and the main ground line VG1 is connected to the ground, so as to activate the current path 2.
In the above mentioned semiconductor memory, at least four block selection lines (S1, S2, S3, S4) are required for each one memory cell bank, for the purpose of limiting the current path flowing through the memory cell to be selected, to only one, in order to read the information of the memory cell. Therefore, the area of the memory bank is increased.
Japanese Patent Application Laid-open Publication No. IP-A-063-18683 and its corresponding European Patent Publication No. 0 627 742 A2, the disclosure of which is incorporated by reference in its entirety into this application, discloses a second conventional semiconductor memory having a memory cell bank structure. In this second conventional semiconductor memory, by changing the amount of channel ion implantation in memory cell transistors, four different threshold voltages are realized, so that multi-value level ROM cells can be obtained. Three sub-bit lines are connected through three selection transistors, respectively, in common to one main bit line, and two sub-ground lines are connected through two selection transistors, respectively, in common to one main ground line. In addition, the sub-bit lines and the sub-ground lines are alternately arranged, so as to reduce a leakage current when the multi-value level ROM cell is read, and also so as to sufficiently ensure a margin from a reference voltage used at the reading time.
However, this second conventional semiconductor memory is so configured that the five selection transistors are controlled by five independent selection lines, respectively. Accordingly, the second conventional semiconductor memory comprises five selection lines for one memory bank. Therefore, the area of the memory bank is increased, similarly to the first conventional semiconductor memory.